RIGORON
RIGOR EDA
RigorCons timing constraint management software is an automation tool used to constrain and manage SDC throughout multiple steps of digital chip design. The tool can automatically check and verify multiple SDCs in parallel by using the constraints of years of practical experience. Identify gaps and errors in each SDC as early as possible, significantly reduce the time for manual review of the SDC, and shorten the iteration cycle. Avoid the huge losses caused by tape-out, so that designers have more energy to solve more difficult problems. The tool consists of five core engines: Rule-based engine, Formal-based engine, Equivalence engine, Hierarchical engine, Timing Budgeting engine. The tool has worked with SDC files larger than 4GB and has been validated with large customers.
RigorCons Timing Constraint Signoff Management Software
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RigorDRC Design Rule Check signoff software
RigorDRC is a full-scale DRC (Design Rule Check) software, which supports the design rule check for interconnects and cell designs. The ability to support advanced process nodes is more efficient than similar tools and is more suitable for dealing with ultra-large-scale layout. Containing friendly graphical interface, designers can quickly find and repair the violations in the design.
RigorEMIR is a power integrity solution providing high accurate of EM/IR analysis for very large-scale digital circuit design based on modern computing architecture. It includes high performance computing with independent intellectual property rights, distributed computing architecture and multi-physical simulation. Combined with RigorTime engine, it is a full-chip power integrity analysis from RTL to gate level and package, including static/dynamic EM/IR analysis. It also contains a simple and user-friendly GUI, to help designer find out the possible hidden dangers of design in advance and fix them quickly.
RigorEMIR Power Integrity Analysis Signoff Software
RigorTime RigorTime static timing analysis sign-off software
RigorTime is a comprehensive static timing analysis product designed to address the most advanced timing requirements. Including signal integrity (SI) analysis, path-based analysis (PBA), on-chip variation (LVF, OCV), multi-mode and multi-angle analysis (MMMC), Hierarchical analysis, etc. More than just an analysis tool, RigorTime is deeply integrated with the Rigor system. Through the flexible script language, the time sequence sign-off is closely combined with the design flow, and it accelerates the time convergence speed of the whole design process which greatly improves the efficiency.